The present invention relates generally to integrated circuits and in particular the present invention relates to differential input buffer circuits.
Synchronous integrated circuits operate according to an externally supplied clock signal. Internal circuit functions are performed in response to transitions of the clock signal. A differential buffer circuit is typically provided to monitor the clock input signal and produce an output signal indicating the detection of a transition in the clock signal. These differential buffer circuits can also produce complementary output signals where one signal follows the clock signal, and the second signal follows the inverse of the clock signal. These complementary output signals are susceptible to skew. As such, circuitry operating in response to the output signals may require a buffer circuit to reduce the effects of the signal skew.
Referring to the drawings, FIGS. 1 and 2 show a differential buffer circuit generally designated by the numeral 1. Circuit 1 includes p-channel pull-up transistors 3, 7, 5, 15. Circuit 1 also includes n-channel pull-down transistors 9, 11, 13. Circuit 1 further includes a multiplexer 17 connected to bias node 19. Transistor 3 has a source connected to a positive supply voltage Vcc and a drain connected to the bias node 19. The gates of transistors 7 and 9 are connected in common at bias node 19. The gates of transistors 5 and 11 are connected in common at node 21. The gates of transistors 15 and 13 are connected to Vin at node 27. The drain of transistor 7 is connected to the drain of transistor 9 at node 25. The source of transistor 7 is connected to the drain of transistor 5 and the source of transistor 15 at node 29. The source of transistor 5 is connected to a positive supply voltage Vcc. The drains of transistors 15 and 13 are connected to Vout at node 23. The source of transistor 13 is connected to the drain of transistor 11 and the source of transistor 9 at node 31. The source of transistor 11 is connected to the system ground Vss.
When circuit 1 is in power down mode (EN low state), Vcc is applied to the bias node 19 through transistor 3 while the multiplexor 17 is turned off. At this point, p-channel transistor 7 is off while the n-channel transistor 9 is turned on. When circuit 1 exits powerdown (EN high state), the bias node 19 starts to decay down to a midpoint 18, as shown in FIG. 2. Accordingly, due to the bias""s slow decay, the trip point of the buffer circuit 1 is lowered when Vin goes to a high state on the first valid command. This causes an initial premature rising clock edge 20. Hence, by the time the next Vin high arrives, the bias node 19 should be stabilzed and the clock duty cycle becomes symmetrical.
This initial trip point is undesirable since variations in the trip point of a buffer or erroneous changes in state can result in very significant timing errors. This is particularly true in view of the fact that the buffer is frequently used as the first gate on a chip which receives signals external to the chip. For example, in high speed devices, a class of circuits is used that is commonly referred to as Address Transition Detection (ATD) circuits. If the output of a buffer driving an ATD were to change state as a result of voltage variations on the supply line, for example, the ATD would incorrectly initiate a sequence of events in the chip. Hence, these events would disrupt operation of the chip thereby resulting in the creation of more voltage variations and incorrect results.
Hence, what is needed is a differential buffer circuit which overcomes the above-noted shortcomings of conventional differential buffer circuits.
The present invention provides a differential buffer circuit which can be precisely set and is stable with respect to voltage variations while reducing signal skew between output signals. The present invention provides a selectively enabled differential buffer circuit which relies on a bias voltage at a bias node during operation and which includes a pulser circuit which provides a pulsed signal to the bias node in response to an enabling signal for the buffer circuit. The pulser circuit enables the bias node to quickly come to a desired operating voltage when the buffer circuit is first enabled to avoid skewed output signals which might otherwise occur during initial operation of the enabled buffer circuit.
The above advantages and features of the invention will be more clearly understood from the following detailed description which is provided in connection with the accompanying drawings.